1. Field of the Invention
The present invention relates to a pin electronics circuit.
2. Description of the Related Art
In order to test semiconductor devices (which will also be referred to as “devices under test” or “DUTs” hereafter), a test apparatus is used. In order to measure a large number of DUTs at the same time, such a test apparatus includes several hundred to several thousand channels of pin electronics circuits. FIG. 1 is a block diagram which shows a configuration of a typical test apparatus. A test apparatus 1002 includes a pin electronics board 1012 and an unshown performance board. The pin electronics board 1012 and the performance board are connected to each other via a connector 16 and a cable 18. The performance board includes a socket via which the DUT is to be mounted.
The pin electronics board 1012 includes a driver DR configured to output a test signal to the DUT, and a comparator CP configured to receive a signal output from the DUT, and to judge the level of the signal thus received. The driver DR and the comparator CMP are integrated on a pin electronics IC (Integrated Circuit) 1010. A path that connects an I/O pin PI/O of the pin electronics IC 1010 and a given terminal A on the performance board side will be referred to as the “transmission line 20”.
Such a configuration in which the driver DR and the comparator CP are connected to such a shared I/O pin PI/O will also be referred to as a “shared I/O configuration”. Such an architecture having such a shared I/O configuration is capable of switching states between a state in which a test signal is output from the driver DR to the DUT, and a state in which the comparator CP receives a signal output from the DUT. Accordingly, a driver-side switch 22 is arranged between the output terminal of the driver DR and the I/O pin PI/O. When the driver-side switch 22 is turned off, the driver DR is cut off from the DUT and the comparator CP.
A programmable load 30 is arranged in order to change the input impedance of the test apparatus 1002 as viewed from the test apparatus 1002. A load-side switch 24 is arranged in order to allow the programmable load 30 to be connected to and to be cut off from the transmission line 20.
The test apparatus 1002 includes a DC test unit (which will also be referred to as a “Parametric Measurement Unit” or “PMU”) 32, in addition to the pin electronics board 1012. The DC test unit 32 performs a DC test operation for measuring the DC characteristics of the DUT, e.g., leak current.
The pin electronics IC 1010 and the connector 16 are connected to each other via transmission lines (strip lines or microstrip lines) 14a and 14b and an output relay 26. The DC test unit 32 is connected to the connector 16 via a DC relay 28 and the transmission line 14b. The output relay 26 and the DC relay 28 are arranged in order to switch test modes between an AC test mode and a DC test mode. When the output relay 26 is on and the DC relay 28 is off, the DUT is connected to the pin electronics IC 1010, thereby providing an AC test operation. Conversely, when the output relay 26 is off and the DC relay 28 is on, the DUT is connected to the DC test unit 32, thereby providing a DC test operation.
The above is the configuration of the test apparatus 1002. In order to predict a signal waveform output from the pin electronics IC 1010 or a signal waveform input to the pin electronics IC 1010 from the DUT, in the design of such a test apparatus 1002, the following two factors are required to be known.
(1) The device model of the transmission line 20 between the pin electronics IC 1010 and the terminal A (simulation model).
(2) The terminal impedance of the pin electronics IC 1010 side as viewed from the terminal B.